The present invention generally relates to fabrication of semiconductor devices and more particularly to an epitaxial growth of a compound semiconductor layer such as gallium arsenide on a silicon wafer.
Gallium arsenide (GaAs) is a typical compound semiconductor material used for laser diodes and various fast speed semiconductor devices such as metal-semiconductor field effect transistor (MESFET), high electron mobility transistor (HEMT), heterojunction bipolar transistor (HBT) and the like because of its characteristic band structure and high electron mobility. Such a semiconductor device is constructed on a gallium arsenide wafer sliced from a gallium arsenide ingot grown as a single crystal or on a gallium arsenide substrate grown epitaxially on a surface of a silicon wafer. In the latter construction, one can avoid the difficulty of handling heavy and brittle gallium arsenide wafer during the fabrication process of the device by using a light and strong silicon wafer fabricated by a well established process for the base of the substrate. Further, one can easily obtain a large diameter wafer in such a construction. As a result, one can handle the wafer easily and reduce the manufacturing cost of the device. Further, such a wafer is suited for fabrication of a so called optoelectronic integrated circuit (OEIC) devices wherein gallium arsenide laser diode and the like are assembled together with silicon transistors on a common semiconductor chip.
When growing gallium arsenide on silicon wafer epitaxially, however, one encounters various difficulties. Such difficulties are caused mainly due to large difference in the lattice constant and thermal expansion between silicon and gallium arsenide. For example, the lattice constant of silicon is smaller than that of gallium arsenide by about 4% and the thermal expansion coefficient of silicon is smaller than that of gallium arsenide by about 230%. From simple calculation based on the difference in the lattice constant, it is predicted that the gallium arsenide substrate constructed as such contains dislocations with a density in the order of 10.sup.12 /cm.sup.2. Thus, a simple epitaxial growth of gallium arsenide layer made directly on silicon substrate is usually unsuccessful. Even if successful, such a layer involves significant defects such that they cannot be used as the substrate for a semiconductor device.
In order to eliminate these problems and obtain a gallium arsenide substrate layer having a quality satisfactory for a substrate of semiconductor device, it is proposed to interpose a buffer layer between the silicon wafer and the gallium arsenide substrate so as to absorb any stress caused as a result of mismatch in the lattice constant and thermal expansion between the wafer and the substrate. In one example, a super lattice layer is used for the buffer layer wherein a plurality of crystal layers each containing a few layers of atoms and having its own lattice constant which is different from each other are stacked on the surface of the silicon wafer before the deposition of the gallium arsenide substrate. By doing so, propagation of defects into the gallium arsenide substrate layer is prevented. Unfortunately, the formation of such a super lattice structure requires an extremely precise control of the crystal growth which is difficult to achieve with reliability in the presently available technique.
Alternatively, it is proposed to interpose a polycrystalline gallium arsenide buffer layer between the silicon substrate and the gallium arsenide layer to absorb the mismatching of the lattice constant and thermal expansion. In this approach, a thin gallium arsenide polycrystalline buffer layer having a thickness of typically 10 nm is deposited on the silicon substrate at a temperature of about 400.degree.-450.degree. C. prior to deposition of the single crystal gallium arsenide substrate layer. Then, the temperature is raised to about 600.degree.-750.degree. C. and the gallium arsenide substrate layer is deposited for a thickness of about a few microns. When the temperature is raised from the first temperature to the second temperature, the polycrystalline gallium arsenide buffer layer is recrystalized into single crystal and the gallium arsenide substrate layer deposited thereon grows while maintaining epitaxial relation with the gallium arsenide buffer layer underneath.
In this technique, however, it is difficult to obtain a satisfactorily flat surface for the single crystal gallium arsenide layer. This is because the polycrystalline gallium arsenide buffer layer takes an island structure on the surface of the silicon wafer and the non-flat morphology of the surface of the polycrystalline gallium arsenide buffer layer is transferred to the gallium arsenide substrate layer provided thereon. In other words, the surface of the gallium arsenide substrate layer becomes waved in correspondence to the island structure of the buffer layer. In spite of the use of reduced temperature at the time of formation of the buffer layer so as to suppress the formation of the island structure by reducing the growth rate, the island structure cannot be eliminated satisfactorily. Further, such a waved surface of the gallium arsenide substrate cannot be eliminated even if the thickness of the gallium arsenide layer is increased to a few microns or more.
Further, it is proposed to use other material such as silicon-germanium solid solution Si.sub.y Ge.sub.l-y for the buffer layer while changing the composition y continuously from the surface of the silicon substrate to the bottom of the gallium arsenide substrate layer as is described in the Japanese Laid-open Patent Application No. 62-87490. Alternatively, it is proposed to use a gallium arsenide based mixed crystal such as In.sub.x Ga.sub.l-x As or Al.sub.x Ga.sub.l-x As with a composition x of about 4.5.times.10.sup.-3 for the buffer layer (Japanese Laid-open Patent Application No. 62-291909). In both of these alternatives, there is a problem in the surface morphology as already described.
On the other hand, the applicants made a discovery during a series of experiments to deposit a group III-V compound such as aluminium arsenide (AlAs) on a gallium arsenide substrate by atomic layer epitaxy (ALE) that aluminium deposited on an arsenic plane of the gallium arsenide substrate rapidly covers the surface of the substrate with a surface density corresponding to two or three molecular layers of the group III-V compound (U.S. patent application Ser. No. 172,671; Ozeki et al., J.Vac.Sci.Tech.B5(4), Jul/Aug 1987 pp.1184-1186). Further, it was found that there is a saturation or self-limiting effect in the deposition of aluminium arsenide. More specifically, there occurs substantially no additional deposition of aluminium after it is deposited on the surface of gallium arsenide for a surface density corresponding to two or three molecular layers of aluminium arsenide. In this study, however, it was not clear if such a self-limiting effect appears also when aluminium arsenide is deposited on the surface of silicon having diamond structure instead of the arsenic plane of gallium arsenide having zinc blende structure.
In the present invention, the applicants studied the hetero-epitaxial growth of group III-V compounds on silicon and discovered that epitaxial growth of a group III-V compound comprising at least one element having a strong affinity with silicon can successfully eliminate the formation of the island structure when the compound is grown on silicon in a form of alternating atomic layers of the component elements.